System Verilog Constraint interview Questions
1) What is the most common reason why bugs are missed during the testing of the RTL design? 2) What is Randomization explain briefly? 3) Write a constraint to generate a random value for a ver1 [7:0] within 50 and var2 [7:0] with the non repeated value in every randomization? 4) What is the maximum range of randc variable most of the simulator can support? (Note:- some simulator support more) 5) Write a constraint without an inside function to generate vari value within the range of 34 to 43? 6) Why curly braces used in below constraint? Constraint c1 {a==110; b==3;} 7) When the randomize function will give return value as zero? 8) How to randomize variable which is not labeled rand? 9) ...